Electrostatic discharges (ESD) can result in very high voltages which can destroy electrical equipment and, in particular, its components. An ESD protection apparatus or an ESD protection circuit is therefore required, which offers protection against such overvoltage spikes.
An electrical discharge (charging) may, for example, be caused by direct contact (for example, by being touched by a person or machine), or may be induced by another electrostatic field (for example, lightning strike).
FIG. 1 shows a simplified equivalent circuit for a typical ESD protection apparatus and protection circuit. As shown in FIG. 1, an ESD protection apparatus such as this comprises two ESD protection diodes D1 and D2, which ensure the actual ESD immunity at the input IN and output OUT, with a resistance R for the low-pass filter being connected in parallel for this purpose. The capacitive effect of the ESD protection diodes D1 and D2 together with the resistance R forms an RC low-pass filter. This makes it possible, for example, to filter out undesirably high frequencies, thus advantageously making it possible to reduce interference noise.
Furthermore, as shown in FIG. 1, a GND diode D3 can optionally be connected to the first and/or second ESD protection diodes D1 and D2 and can be connected to the ground output GND, thus making it possible to deliberately reduce parasitic capacitances of the protection diodes D1 and D2 resulting from the capacitive series circuit.
ESD protection apparatuses such as these, therefore allow protection in the event of inadvertent contact (for example, charge transfer) with a person, inadvertent contact with machines during a production process, or inadvertent autonomous discharge in the event of contact with a person or machine, during which process the component may itself be electrostatically charged.
As shown in FIG. 1, the ESD protection diodes D1 and D2 are reverse-biased in a range from about −0.6V (diffusion voltage) to about +9V (breakdown voltage), for example, when using silicon semiconductor technology. Since the voltage is between these two values during normal operation of the electrical equipment and of the associated components to be protected, no current flows via the ESD protection diodes D1 and D2 in the normal situation. However, if, for example, a considerably higher voltage than the operating voltage is applied to the input IN of the ESD protection apparatus (for example, lightning or electrostatic discharge), then the ESD protection diodes D1 and D2 changeover to the breakdown region. To be more precise, a current now flows away mainly via the diodes because of their low internal resistance thus protecting, for example, not only the components or electrical devices which are connected to the output OUT but also those connected to the input IN against the ESD pulse, and the damage resulting from it. In this case, the ESD immunity of the ESD protection apparatus itself, that is to say, of the ESD protection diodes D1 and D2 contained in it, is the critical factor for the ESD immunity of the overall circuit.
Furthermore, the performance features of an ESD protection apparatus often directly contradict one another. For example, on the one hand the ESD immunity, that is to say, the resistance to overvoltages, furthermore the crosstalk response between individual channels of a circuit and, finally, the (overall) line capacitance may be mentioned as significant performance features of an ESD protection apparatus, which influence one another and are unfortunately mutually contradictory. If, in consequence, the areas of the ESD protection diodes are increased, then the ESD immunity admittedly increases, but the overall line capacitance also increases at the same time.
The GND diode D3 introduced for this purpose in FIG. 1 can admittedly lead to a reduction in the total capacitance, but in turn lead to greater crosstalk between the individual channels of the ESD protection apparatus.
FIGS. 2 and 3 respectively show a plan view and a sectional view of a conventional ESD protection circuit, as may be provided as an integrated semiconductor circuit. As shown in FIG. 1, the conventional ESD protection circuit has four channels, each having two ESD protection diodes D11 and D21, D12 and D22, D13 and D23, as well as D14 and D24. Furthermore, each channel has a resistance R11, R22, R33 and R44, which are each connected via interconnects 60 to the ESD protection diodes and are in the form of a diffusion resistance in a semiconductor substrate 10 as shown in FIG. 3.
Furthermore, two GND diodes D31 and D33 are formed in the semiconductor substrate and connect the rear-face connections of the ESD protection diodes, and the semiconductor substrate, to the ground output GND (or to ground potential +0.6V diffusion voltage).
FIG. 3 shows a section view of a channel of the ESD protection circuit illustrated in FIG. 2, with identical reference symbols denoting identical or corresponding elements.
As shown in FIG. 3, n-doped, for example, doping regions 20 and 30 are formed in a p-doped silicon semiconductor substrate 10 in order to provide ESD protection diodes D11 and D21. Furthermore, an n-doped doping region 40 is formed in the semiconductor substrate 10 in order to provide the associated ESD protection resistance R11. The first ESD protection diode D11 is in this case connected to the input IN and also to one connection of the protection resistance R11 via an interconnect 60. In addition, the further connection of the protection resistance R11 is connected via a further interconnect to the second ESD protection diode D21 and to the output OUT. The semiconductor substrate 10 may also be connected to the GND pad, via the GND diode D31, at a point (which is not illustrated) in the semiconductor substrate.
In the event of an ESD load (for example, a lightning strike or overvoltage), for example, at the input IN, the current is actually intended to be dissipated via the ESD protection diode D11 into the semiconductor substrate 10 in order to protect an appliance or component connected to the output OUT. However, as can easily be seen from FIG. 3, the current will not only flow away via the ESD protection diode D11 into the semiconductor substrate 10, but will also flow via the interconnect 60 to the resistance R11, where it will likewise flow away into the semiconductor substrate 10 via a parasitic diode DR (Diode Resistor) that is created in the input area of the resistance R11. One reason for this is that the path resistance of the interconnect 60 is normally less than the internal resistance of the diode. In consequence, a portion of the current flows via the interconnect 60, thus reaching the additional parasitic diode DR at the input-side pn-junction of the protection resistance R11. At the output end of the diffusion resistance R11, the current and the power in the event of ESD will have already been greatly reduced, so that the ESD immunity at the output pn junction is no longer critical.
In consequence, the pn junction of the parasitic diode DR will in fact be destroyed by lower ESD voltages than in the case of a dedicated ESD protection diode D11, although the incoming portion of the current is only a portion of the total current which flows via the protection circuit. The reason for the destruction at this point is that the parasitic diode DR adjacent to the diffusion resistance R11 does not represent a specially designed ESD diode (layout design), but is created inadvertently by the input pn junction between the n-doped region 40 of the diffusion resistance R11 and the p semiconductor substrate 10. In consequence, this pn junction breaks down at a much lower load than would be the case with the ESD protection diode D11.
This problem, which is essentially the result of the fact that the protection resistance R11 is in the form of an integrated semiconductor resistance (or diffusion resistance) in the semiconductor substrate, and a pn junction therefore acts as a diode which in turn represents a weakness, has normally been solved by means of a protection resistance (outside the semiconductor substrate) which is independent of the semiconductor substrate and is in the form of a poly-resistance which, for example, is formed above the semiconductor substrate, separated from the semiconductor substrate by a field oxide. However, this solution requires a plurality of additional masks, thus in turn involving increased costs.
There is therefore a requirement to provide an overvoltage protection apparatus and an associated protection circuit with better characteristics and lower cost.